This the most basic type of field effect transistor and is often just referred to simply as a FET. The term unipolar, refers to the fact that there is only one type of majority charge carrier involved in the current flow through the device. (Unlike the bipolar transistor, which involves the flow of both electrons and holes).
The FET has three terminals, the Source, the Gate and the Drain . The circuit symbol for an N channel FET is shown below. When a voltage is applied between the source and drain current will flow. However with a suitable voltage applied between the gate and source the current flowing from drain to source can be controlled, (similar to the way that the base current controls the collector current in a bipolar transistor). Therefore the FET, like the bipolar transistor, can be used both as a switch and as a signal amplifier. Each device has advantages and disadvantages compared to the other when used in these applications. We will consider these later, but first we will focus on how the FET operates. We will consider an N channel FET, however the same principles can be used to describe a P channel FET. The only differences are that holes are the current carriers in a P channel FET, (as opposed to electrons for the N channel FET) and the voltage between the gate and source have opposite polarity for each.
The operation of the FET is much simpler to understand than a bipolar transistor. This is described below and illustrated in the following diagrams.
Referring to the diagrams above, the gate terminal is actually in contact with both of the P type regions, however this connection is not shown in the diagrams. If a voltage is applied between the source and drain, then current will flow because the N channel between these two terminals provides a highly conductive path. However, when a voltage is applied between the gate and source ( VGS ) as shown, this will reverse bias the PN junctions. This extends the depletion layers and therefore reduces the cross sectional area of the conducting channel. This in turn would reduced the current flowing from drain to source ID. It is clear therefore, that by controlling VGS, we can control the current between the drain and source ID. The second diagram shows how the conducting channel is narrowed further when VGS is increased. If we continued to increase VGS then eventually ID will reduce to zero, when the depletion region extends completely across the N channel. The value of VGS that this occurs at is called the cut off voltage VGS(off).
A P channel FET works in a similar manner except that holes are the majority current carriers involved and the polarity of VGS must be the opposite to that applied to an N channel. The circuit symbol for a P channel FET is shown below.
As described above, for a fixed drain to source voltage, ID will be at its greatest when VGS is zero. Then as VGS is increased, ID decreases reaching 0 at VGS(off). i.e. The application of VGS reduces the FETs conduction properties. A FET that behaves this way is called a depletion type FET.
